1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device and methods thereof, and more particularly to a semiconductor memory device and methods of reading data from the semiconductor memory device.
2. Description of the Related Art
A synchronous dynamic random access memory (DRAM) (SDRAM) may conform with standards developed by the Joint Electron Device Engineering Circuit (JDEC). Typically, SDRAMs may be characterized by having 1) input/output (I/O) circuit synchronized with an external clock, 2) burst access, 3) multi-bank configuration, 4) command-type access, and 5) data path using pipeline technique, which are described below in greater detail.
With regard to I/O circuit synchronization, SDRAM may establish various timing parameters in multiples of a clock cycle in order to input and output signals in synchronization with an external clock. Because a control signal applied during a single clock cycle may be stored in an internal register, a received state may be maintained until the contents in the internal register are changed. A control signal (e.g., different from the clock signal) may be received in order to change the received state. For example, two or more control signals may be provided and an operating state of the SDRAM may be determined based on a status of each of the control signals. The state may be decoded by a command decoder in the SDRAM, such that other operations of the SDRAM may be performed. Accordingly, adjusting the state or start-point of an operation may be considered as a type of programming, typically referred to as a command.
With regard to burst access, a burst may generally refer to any phenomenon with a relatively high intensity and a relatively short duration. As used herein, the burst access may indicate that data input/output of a memory may be successively performed in synchronization with a clock. If an active command ACT_CMD and a row address are received at a rising edge of a clock, a memory may transition to an activated state (e.g., a first logic level, such as a higher logic level or logic “1”) and a word line may be selected by the row address. If a read command and a column address are received at the following clock, a burst operation may be carried out. Thus, a column address may be increased or incremented after a given number of clock cycles, and data may be successively or consecutively outputted.
A bank may include a plurality of memory cells that may operate independently in order to achieve a higher-speed operation via interleaving in a memory module. Memory cells in one bank may typically share both a data bus as well as address and control signal lines in common, and may operate independently with respect to another bank (e.g., each bank may have its own connection buses). Accordingly, while a data read operation may be performed with respect to a first bank, a precharge or refresh operation may be performed with respect to a second bank or a word line selecting operation may be carried out by a row address.
A pipeline may refer to a concurrent data handling structure or process wherein a data path may be divided using flip-flops or latches and a plurality of circuit blocks may be operated concurrently. That is, a data path may be divided into a plurality of independent circuit blocks by disposing two or more flip-flops or latches on the data path. Read data may be latched by one circuit block, and the latched data may be outputted to an external entity via another path. Concurrently, a new address may be received through another path or a precharge operation may be carried out.
Double Data Rate (DDR) SDRAM may input and output data or commands at both rising and falling edges of a clock. Accordingly, in an example, a data rate corresponding to a clock of 200 MHz (e.g., of a single data rate (SDR) SDRAM) may be achieved using a clock of 100 MHz. To achieve such a result, the clock signal may be set to have a duty of 50%.
The DDR SDRAM may be classified as one of DDR1 SDRAM, DDR2 SDRAM, DDR3 SRAM, etc. The DDR1 SRAM may utilize a 2-bit pre-fetch manner at input/output and may have a data burst length of 2. The DDR2 SRAM may utilize a 4-bit pre-fetch manner at input/output and may have a data burst length of 4. The DDR3 SRAM may utilize an 8-bit pre-fetch manner at input/output and may have a data burst length of 8. Herein, if a burst length is 8, then eight data may be successively inputted and outputted via one input/output terminal in synchronization with a single clock, and so on.
The DDR3 SDRAM may support a read leveling operation, which may refer to adjusting a DQS skew between a chipset and a memory chip by transferring data patterns set in a register of the memory chip to the chipset. An operation for reading the data patterns in the register may be carried out irrespective of whether normal data is stored in memory cells. Such an operation may be referred to as a “special” read operation, in contrast to a “normal” read operation.
As set forth above, the SDRAM may include data patterns read irrespective of whether normal data is stored in memory cells. The special read operation may typically be performed in order to read these data patterns. The special read operation may be said to be “indifferent” to the presence of normal data. However, data access operations such as a word line enable operation, a bit line precharge operation, may still be performed during special read operations, which may increase a duration of special read operations as well as a power consumption of the special read operations.